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MT9072AB 데이터시트(PDF) 197 Page - Zarlink Semiconductor Inc

부품명 MT9072AB
상세설명  Octal T1/E1/J1 Framer
PDF  275 Pages
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제조업체  ZARLINK [Zarlink Semiconductor Inc]
홈페이지  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB 데이터시트(HTML) 197 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
197
Zarlink Semiconductor Inc.
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EEL15
EEL14
EEL13
EEL12
EEL11
EEL10
EEL9
EEL8
EEL7
EEL6
EEL5
EEL4
EEL3
EEL2
EEL1
EEL0
E-bit Error Count Latch. These bits make up a latch which samples the
current value of the E-Bit Error Counter (address Y17) on the rising edge of
the internal one second timer (ONESEC register address Y11). This latch is
cleared with a RESET (RESET pin or RST bit). EEL0 is the least significant
bit (LSB).
Table 173 - E-Bit Error Count Latch (R Address Y28) (E1)
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VEL15
VEL14
VEL13
VEL12
VEL11
VEL10
VEL9
VEL8
VEL7
VEL6
VEL5
VEL4
VEL3
VEL2
VEL1
VEL0
Bipolar Violation (BPV) Error Count Latch. These bits make up a latch
which samples the current value of the Bipolar Violation (BPV) Error Counter
(address Y18) on the rising edge of the internal one second timer (ONESEC
register address Y11). This latch is cleared with a RESET (RESET pin or RST
bit). VEL0 is the least significant bit (LSB).
Table 174 - Bipolar Violation (BPV) Error Count Latch (R/W Address Y29) (E1)



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