MT9072AB datasheet(207/275 Pages) ZARLINK

207 / 275 page

MT9072

Data Sheet

207

Zarlink Semiconductor Inc.

CSYNCM

(0)

Receive CRC-4 Synchronization Mask. This is the mask bit for the CSYNCI interrupt status

bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register

(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this

mask bit is zero, the corresponding interrupt bit will function normally.

MSYNCM

(0)

Receive Multiframe Alignment Mask. This is the mask bit for the MSYNCI interrupt status

bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register

(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this

mask bit is zero, the corresponding interrupt bit will function normally.

BSYNCM

(0)

Receive Basic Frame Alignment Mask. This is the mask bit for the BSYNCI interrupt status

bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register

(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this

mask bit is zero, the corresponding interrupt bit will function normally.

Bit

Name

Functional Description

not used.

SLOM

(0)

Loss of Sync Counter Overflow Mask. This is the mask bit for the SLOI interrupt status bit

in the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

FEOM

(0)

Frame Alignment Signal (FAS) Error Counter Overflow Mask. This is the mask bit for the

FEOI interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt

Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit will

remain inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.

FEIM

(0)

Frame Alignment Signal (FAS) Error Counter Indication Mask. This is the mask bit for the

FEII interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt

Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit will

remain inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.

BEOM

(0)

Frame Alignment Signal (FAS) Bit Error Counter Overflow Mask. This is the mask bit for

the BEOI interrupt status bit in the Counter (Counter Indication and Counter Overflow)

Interrupt Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit

will remain inactive. If this mask bit is zero, the corresponding interrupt bit will function

normally.

BEIM

(0)

Frame Alignment Signal (FAS) Bit Error Counter Indication Mask. This is the mask bit for

the BEII interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt

Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit will

remain inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.

9CEOM

(0)

CRC-4 Error Counter Overflow Mask. This is the mask bit for the CEOI interrupt status bit in

the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

Table 183 - Counter (Counter Indication and Counter Overflow) Interrupt Mask Register (Address Y45)

(E1)

Bit

Name

Functional Description

Table 182 - Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Mask Register (Address Y44)

(E1)

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