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MT9072AB 데이터시트(PDF) 243 Page - Zarlink Semiconductor Inc

부품명 MT9072AB
상세설명  Octal T1/E1/J1 Framer
PDF  275 Pages
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제조업체  ZARLINK [Zarlink Semiconductor Inc]
홈페이지  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB 데이터시트(HTML) 243 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
243
Zarlink Semiconductor Inc.
Figure 28 - Motorola Microprocessor Timing
‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1. High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
AC Electrical Characteristics - Intel Microprocessor Timing*
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1RD low
tRDL
115
ns
2RD High
tRDH
50
ns
3CS Setup
tCSS
0ns
4CS Hold
tCSH
0ns
5WR low
tWRL
70
ns
6WR High
tWRH
50
ns
7
Address Setup
tADS
15
ns
8
Address Hold
tADH
40
ns
9
Data Delay Read
tDDR
100
ns
CL = 150 pF, RL = 1 kΩ.
10
Data Hold Read
tDHR
5ns
CL = 150 pF, RL = 1 kΩ
11
Data Active to High Z Delay
tDAZ
50
ns
CL = 150 pF, RL = 1 kΩ, Note
1
12
Data Setup Write
tDSW
15
ns
13
Data Hold Write
tDHW
25
ns
14
Cycle Time
tCYC
165
MT9072
Outputs Data
tCSS
tRWS
tADS
tCSH
tRWH
tADH
tDHR
tDDR
tDSH
tDSL
tDAZ
Note: DS and CS may be connected together.
tCYC
VT
VT
VT
VT
VT
T
MT9072
Inputs Address
DS (RD)
CS
R/W (WR)
A0-10
D0-15
READ
V
MT9072
InputsData
D0-15
WRITE
tDSW
tDSH



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