PM6344 datasheet(55/256 Pages) PMC

55 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

conversion of each data byte, an interrupt is generated to signal the controller to

write the next byte into the Transmit Data Register. After the last data frame byte

is transmitted, the CRC word (if CRC insertion has been enabled), or a flag (if

CRC insertion has not been enabled) is transmitted. The XFDL then returns to

the transmission of flag characters.

If there are more than five consecutive ones in the raw transmit data or in the

CRC data, a zero is stuffed into the serial data output. This prevents the

unintentional transmission of flag or abort characters.

Abort characters can be continuously transmitted at any time by setting a control

bit. During transmission, an underrun situation can occur if data is not written to

the Transmit Data Register before the previous byte has been depleted. In this

case, an abort sequence is transmitted, and the controlling processor is notified

via the TDLUDR signal. Optionally, the interrupt and underrun signals can be

independently enabled to also generate an interrupt on the INTB output,

providing a means to notify the controlling processor of changes in the XFDL

operating status.

When the internal HDLC transmitter is disabled, the serial data to be transmitted

on data link can be input on the TDLSIG pin timed to the clock rate output on the

TDLCLK pin.

8.12 Digital Jitter Attenuator (DJAT)

The Digital Jitter Attenuation function is provided by the Digital Jitter Attenuator

(DJAT) block. The DJAT block receives jittered E1 data in NRZ format from TRAN

on two separate inputs, which allows bipolar violations to pass through the block

uncorrected. The incoming data streams are stored in a FIFO timed to the

transmit clock (either BTCLK[x] or RCLKO[x]). The respective input data emerges

from the FIFO timed to the jitter attenuated clock (TCLKO[x]) referenced to either

TCLKI[x], BTCLK[x], or RCLKO[x].

The jitter attenuator generates the jitter-free 2.048 MHz TCLKO[x] output transmit

clock by adaptively dividing the 49.152 MHz XCLK signal according to the phase

difference between the generated TCLKO[x] and input data clock to DJAT (either

BTCLK[x] or RCLKO[x]). Fluctuations in the phase of the input data clock are

attenuated by the phase-locked loop within DJAT so that the frequency of

TCLKO[x] is equal to the average frequency of the input data clock. Phase

fluctuations with a jitter frequency above 8.8 Hz are attenuated by 6 dB per

octave of jitter frequency. Wandering phase fluctuations with frequencies below

8.8 Hz are tracked by the generated TCLKO[x]. To provide a smooth flow of data

out of DJAT, TCLKO[x] is used to read data out of the FIFO.

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