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WM8608 데이터시트(PDF) 10 Page - Wolfson Microelectronics plc |
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WM8608 데이터시트(HTML) 10 Page - Wolfson Microelectronics plc |
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10 / 54 page ![]() WM8608 Product Preview w PP Rev 1.5 March 2004 10 AUDIO INTERFACE TIMING – MASTER MODE BCLK (Output) LRCLK (Output) t DL DINFRONT DINSRND DINC_LFE DINREAR t DHT t DST Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge tDL 10 ns DINFRONT, DINSRND, DINC_LFE and DINREAR setup time to BCLK rising edge tDST 10 ns DINFRONT, DINSRND, DINC_LFE and DINREAR hold time from BCLK rising edge tDHT 10 ns Table 4 Audio Interface Timing – Master Mode |
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