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WM8608 데이터시트(PDF) 17 Page - Wolfson Microelectronics plc

부품명 WM8608
상세설명  5 TO 7.1 CHANNEL PWM CONTROLLER
PDF  54 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8608 데이터시트(HTML) 17 Page - Wolfson Microelectronics plc

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WM8608
w
PP Rev 1.5 March 2004
17
multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as
a timing reference to indicate the beginning or end of the data words.
In left justified, right justified and I
2S modes, the minimum number of BCLKs per DACLRC period is 2
times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low
for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the
above requirements are met.
In DSP mode A or B, all channels are time multiplexed onto DINFRONT. LRCLK is used as a frame
sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period
is 8 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the
rising edge is correctly positioned (see Figure 9, Figure 10 and Figure 11).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCLK following a LRCLK
transition. LRCLK is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DINFRONT
DINSRND
DINC_LFE
DINREAR
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 9 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.
LRCLK is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DINFRONT
DINSRND
DINC_LFE
DINREAR
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 10 Right Justified Mode Timing Diagram



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