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WM8608 데이터시트(PDF) 18 Page - Wolfson Microelectronics plc |
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WM8608 데이터시트(HTML) 18 Page - Wolfson Microelectronics plc |
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18 / 54 page ![]() WM8608 Product Preview w PP Rev 1.5 March 2004 18 I 2S MODE In I 2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition. LRCLK is low during the left samples and high during the right samples. LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DINFRONT DINSRND DINC_LFE DINREAR 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB 1 BCLK 1 BCLK Figure 11 I 2S Mode TIming Diagram DSP MODE A AND B In DSP mode, the Front Left (FL) channel MSB is available on either the 1 st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. LRCLK BCK DINFRONT Input Word Length (IWL) 1/fs DINFRONT LEFT n 2 1 n-1 LSB MSB n 2 1 n-1 DINFRONT RIGHT 2 1 DINSRND LEFT n n-1 DINREAR RIGHT NO VALID DATA 1 BCLK 1 BCLK Figure 12 DSP Mode A Timing Diagram LRCLK BCK DINFRONT Input Word Length (IWL) 1/fs DINFRONT LEFT n 2 1 n-1 LSB MSB n 2 1 n-1 DINFRONT RIGHT 2 1 DINSRND LEFT n n-1 DINREAR RIGHT NO VALID DATA 1 Figure 13 DSP Mode B Timing Diagram |
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