전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

WM8608 데이터시트(PDF) 20 Page - Wolfson Microelectronics plc

부품명 WM8608
상세설명  5 TO 7.1 CHANNEL PWM CONTROLLER
PDF  54 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8608 데이터시트(HTML) 20 Page - Wolfson Microelectronics plc

Back Button WM8608 Datasheet HTML 16Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 17Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 18Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 19Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 20Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 21Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 22Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 23Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 24Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 54 page
background image
WM8608
Product Preview
w
PP Rev 1.5 March 2004
20
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master/slave mode are summarised
below. MS selects audio interface operation in master or slave mode. In Master mode BCLK and
LRCLK are outputs and the frequency of LRCLK is set by the sample rate control bits SR[3:0]. In
Slave mode BCLK and LRCLK are inputs (refer to Table 12 for sample rate control in this case).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
8
BCLKINV
0
BCLK invert bit (for master and slave
modes)
0 = BCLK not inverted
1 = BCLK inverted
7
MS
0
Master / Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
6
LRSWAP
0
Left/Right channel swap
1 = swap left and right data in audio
interface
0 = output left and right data as normal
5
SUBSWP
0
Front Centre – LFE channel swap
1 = Front Centre right and LFE left
0 = Front Centre left and LFE right
Right, left and I
2S modes – LRCLK
polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
(as show in e.g. Figure 12)
4
LRP
0
DSP Mode – A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
3:2
WL[1:0]
10
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
R2 (02h)
Audio IF
Format
1:0
FORMAT[1:0]
10
Audio Data Format Select
11 = DSP Mode
10 = I
2S Format
01 = Left justified
00 = Right justified
Table 11 Audio Data Format Control
Notes:
1.
Right Justified mode does not support 32-bit data.
2.
LRSWAP does not affect the polarity of SUBSWP, the left-right controlling of DINC_LFE is
separate from the other channels.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com