WM8608 datasheet(24/54 Pages) WOLFSON

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WM8608

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PP Rev 1.5 March 2004

SYNCHRONISER

The WM8608 contains a synchroniser circuit to support the synchronisation of an external LRCLK to

the local LRCLK. This mode is only supported in MPEG mode.

The specification of the synchroniser circuit is:

Test Conditions

AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25

oC, f

XIN = 27MHz, Slave Mode, fs = 48kHz, 24-bit data,

unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Lock time

tlock

LRCLK frequency offset

foffLRCLK

±1000

±10’000

ppm fs

0.2

ppm/s

LRCLK drift in Lock

driftLRCLK

Table 15 Synchroniser Specification

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

SYNCEN

Synchroniser Enable

0: Disable

1: Enable (in MPEG mode only)

2:1

GMIN[1:0]

Minimum Synchroniser Gain

00: minimum gain = 2

01: minimum gain = 2

10: minimum gain = 2

11: minimum gain = 2

4:3

GMAX[1:0]

Maximum Synchroniser Gain

00: maximum gain = 2

01: maximum gain = 2

10: maximum gain = 2

11: maximum gain = 2

R32 (20h)

Synchroniser

(1)

HOLD

Hold Synchroniser (and SR detect)

1 : Synchroniser in hold mode

Table 16 Synchroniser (1)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R33 (21h)

Synchroniser

(2)

2:0

SYNTO[2:0]

100

Synchroniser Gain time-out

000: 0.2 ms

001: 0.5 ms

010: 1 ms

011: 2 ms

100: 5 ms (default)

101: 10 ms

110: 20 ms

111: 50 ms

Table 17 Synchroniser (2)

The next table illustrates recommendation for the Synchroniser loop gain G (see also Table 16) and

time-out time (Table 17) with respect to the LRCLK frequency and the resulting Synchroniser lock

time.

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