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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8608 데이터시트(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8608 데이터시트(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 54 page  Product Preview WM8608 w PP Rev 1.5 March 2004 11 AUDIO INTERFACE TIMING – SLAVE MODE BCLK LRCLK t BCH t BCL t BCY DINFRONT DINSRND DINC_LFE DINREAR t LRSU t DS t LRH t DH Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns BCLK rise/fall times 5 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns LRCLK rise/fall times 5 ns DINFRONT, DINSRND, DINC_LFE and DINREAR hold time from BCLK rising edge tDH 10 ns Table 5 Audio Interface Timing – Slave Mode Note: BCLK period should always be greater than or equal to MCLK period. |
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