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WM8778SEDS/R 데이터시트(PDF) 40 Page - Wolfson Microelectronics plc |
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WM8778SEDS/R 데이터시트(HTML) 40 Page - Wolfson Microelectronics plc |
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40 / 50 page ![]() WM8778 Product Preview w PP Rev 1.7 June 2004 40 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 DEEMP 0 De-emphasis Mode Select: 0 : Normal Mode 1: De-emphasis Mode DZFM ZFLAG1 ZFLAG2 R9 (09h) 0001001 DAC Control 2:1 DZFM 00 00 01 10 11 disabled left channels zero both channels zero either channel zero disabled right channels zero both channels zero either channel zero 1:0 DACFMT[1:0] 10 DAC Interface Format Select: 00: right justified mode 01: left justified mode 10: I 2S mode 11: DSP mode DACLRC Polarity or DSP Early/Late Mode Select 2 DACLRP 0 Left Justified / Right Justified / I 2S: 0: Standard DACLRC Polarity 1: Inverted DACLRC Polarity DSP Mode: 0: Early Mode 1: Late Mode 3 DACBCP 0 DAC BITCLK Polarity: 0: Normal – DIN and DACLRC sampled on rising edge of DACBCLK. 1: Inverted - DIN and DACLRC sampled on falling edge of DACBCLK. R10 (0Ah) 0001010 DAC Interface Control 5:4 DACWL[1:0] 10 DAC Input Word Length: 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) 1:0 ADCFMT[1:0] 10 ADC Interface Format Select: 00: right justified mode 01: left justified mode 10: I 2S mode 11: DSP mode ADCLRC Polarity or DSP Early/Late mode select 2 ADCLRP 0 Left Justified / Right Justified / I 2S: 0: Standard ADCLRC Polarity 1: Inverted ADCLRC Polarity DSP Mode: 0: Early Mode 1: Late Mode 3 ADCBCP 0 ADC BITCLK Polarity: 0: Normal - ADCLRC sampled on rising edge of ADCBCLK; DOUT changes on falling edge of ADCBCLK. 1: Inverted - ADCLRC sampled on falling edge of ADCBCLK; DOUT changes on rising edge of ADCBCLK. 5:4 ADCWL[1:0] 10 ADC Input Word Length: 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) R11 (0Bh) 0001011 ADC Interface Control 6 ADCMCLK 0 ADCMCLK Polarity: 0: non-inverted 1: inverted |
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