WM8778SEDSSLASHR datasheet(18/50 Pages) WOLFSON

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WM8778

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PP Rev 1.7 June 2004

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN is sampled by the WM8778 on the first rising edge of

DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and

changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge

of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right

samples (Figure 12).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 12 Left Justified Mode Timing Diagram

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN is sampled by the WM8778 on the rising edge of DACBCLK

preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the

falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples

(Figure 13).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 13 Right Justified Mode Timing Diagram

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