WM8778SEDSSLASHR datasheet(30/50 Pages) WOLFSON

30 / 50 page

WM8778

Product Preview

PP Rev 1.7 June 2004

ADC GAIN CONTROL

The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the

analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right.

The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows

further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 14 shows how the

LAG/RAG[7:0]

ATTENUATION

LEVEL (AT

OUTPUT)

ANALOGUE PGA

DIGITAL

ATTENUATION

00(hex)

∞ dB (mute)

-21dB

Digital mute

01(hex)

-103dB

-21dB

-82dB

A4(hex)

-21.5dB

-21dB

-0.5dB

A5(hex)

-21dB

0dB

CF(hex)

0dB

FE(hex)

+23.5dB

0dB

FF(hex)

+24dB

0dB

Table 14 Analogue and Digital Gain Mapping for ADC

In addition a zero cross detect circuit is provided for the input PGA. When ZCLA/ZCRA is set with a

write, the gain will update only when the input signal approaches zero (midrail). This minimises

audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which

will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of

12.288MHz). The timeout clock may be disabled by setting TOD.

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

0000111

Timeout Clock Disable

TOD

Analogue PGA Zero Cross Detect

Timeout Disable

0 : Timeout enabled

1: Timeout disabled

WM8778SEDS/R 데이터시트(PDF) 30 Page - Wolfson Microelectronics plc

WM8778SEDS/R 데이터시트(HTML) 30 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

데이터시트 다운로드

링크 URL