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WM8778SEDS/R 데이터시트(PDF) 31 Page - Wolfson Microelectronics plc

부품명 WM8778SEDS/R
상세설명  24 BIT 192KHZ STEREO CODEC
PDF  50 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8778SEDS/R 데이터시트(HTML) 31 Page - Wolfson Microelectronics plc

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WM8778
w
PP Rev 1.7 June 2004
31
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to
write the same attenuation value to both left and right volume control registers, saving on software
writes. The ADC volume and mute also applies to the bypass signal path.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
LAG[7:0]
11001111
(0dB)
Attenuation Data for Left Channel ADC Gain in 0.5dB steps. See
Table 14.
R14 (0Eh)
0001110
Attenuation
ADCL
8
ZCLA
0
Left Channel ADC Zero Cross Enable:
0: Zero cross disabled
1: Zero cross enabled
7:0
RAG[7:0]
11001111
(0dB)
Attenuation data for right channel ADC gain in 0.5dB steps. See
Table 14.
R15 (0Fh)
0001111
Attenuation
ADCR
8
ZCRA
0
Right Channel ADC Zero Cross Enable:
0: Zero cross disabled
1: Zero cross enabled
6
MUTERA
0
Mute for Right Channel ADC
0: Mute Off
1: Mute on
7
MUTELA
0
Mute for Left Channel ADC
0: Mute Off
1: Mute on
R21 (15h)
0010101
ADC Input Mux
8
LRBOTH
0
Right Channel Input PGA Controlled by Left Channel Register
0 : Right channel uses RAG and MUTERA.
1 : Right channel uses LAG and MUTELA.
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11 (0Bh)
0001011
ADC Control
8
ADCHPD
0
ADC High Pass Filter Disable:
0: High pass filter enabled
1: High pass filter disabled



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