STLED524 datasheet(14/72 Pages) STMICROELECTRONICS

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Electrical characteristics

STLED524

14/72

DocID026217 Rev 1

dCLKOUT

Duty cycle of the clock out signal

fEXT_MAX

Maximum frequency of the

external clock signal

VIN = 2.7 V to 5.5 V

1.25

MHz

dCLKIN

Duty cycle of the external clock

signal

VIN = 2.7 V to 5.5 V

TINTTOEXTCLK

Transition time from internal to

external clock

TCLKEX

Power switches

RDS(on)

P-channel on-resistance (boost)

230

N-channel on-resistance (boost)

130

RDS(on)

P-channel on-resistance (ROW 0

to ROW 4)

500

N-channel on-resistance (ROW 0

to ROW 4)

200

RDS(on)

Bypass switch on-resistance

ILKG-LX

Coil leakage current

VIN = VSW2 = 4.0 V

µA

Time and delay

TCLK

Clock period

1.667

µs

TRTCR

Delay between row rising edge

and column rising edge

TCLK

TRTCF

Delay between column falling

edge and row falling edge

TONMIN

PWM minimum on-time

TONMAX

PWM maximum on-time

510

TFRAME

Frame period

2560

TROW

Row duration

512

Reset

TRST

Minimum pulse width on RESET

100

µs

It is strongly recommended to connect VDD pin to VSUP pin directly.

It is valid only if LED matrix is not farther than 10 cm from the driver, otherwise ceramic capacitors should be connected

between COLx pin and ground to improve ripple.

Table 6. Electrical characteristics (continued)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

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