STLED524 datasheet(48/72 Pages) STMICROELECTRONICS

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STLED524

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DocID026217 Rev 1

OPEN_M = 1, the interrupt generated by open RSET protection is enabled

SHORT_M = 0, the interrupt generated by short RSET protection is disabled

SHORT_M = 1, the interrupt generated by short RSET protection is enabled

STEP_M = 0 the interrupt generated at the beginning of a scroll step is disabled

STEP_M = 1, the interrupt generated at the beginning of a scroll step is enabled

EOSCR_M = 0, the interrupt generated at the end of scroll operation is disabled

EOSCR_M = 1, the interrupt generated at the end of scroll operation is enabled

ROWSC_M = 0, the interrupt generated by row short-circuit is disabled

ROWSC_M = 1, the interrupt generated by row short-circuit is enabled

BSTOK_M = 0, the interrupt generated, when the boost output voltage reaches the target

value, is disabled

BSTOK_M = 1, the interrupt generated, when the boost output voltage reaches the target

value, is enabled

Bits in this register are set when the corresponding interrupt occurs. These bits are latched

and they can only be cleared by reading the register through SPI.

When an interrupt is disabled, the corresponding bit in the latch register is not set.

Bits in the status register are set and reset according to the state of internal signals

(overtemperature, overvoltage etc.). Reading the status register through SPI does not

influence the state of bits.

4.10.2

Overvoltage protection

If the output voltage of boost is higher than the overvoltage protection threshold, the boost is

stopped. OVP bit in the status register is set. The interrupt is generated, if it is enabled and

OVP bit in the latch register is also set and remains latched, until it is read through SPI. If

the output voltage of the boost goes below the overvoltage protection hysteresis, OVP bit in

the status register is reset. The microcontroller decides, whether to start the boost again or

not.

Table 52. Latch register (read only)

Latch

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Add = 41h

BSTOK ROWSC EOSCR

STEP

SHORT

OPEN

THP

OVP

Default

0000

Table 53. Status register (read only)

Status

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Add = 42h

BSTOK

SHORT

OPEN

THP

OVP

Default

000

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