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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72325AR7-Auto 데이터시트(PDF) 85 Page - STMicroelectronics |
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ST72325AR7-Auto 데이터시트(HTML) 85 Page - STMicroelectronics |
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85 / 243 page  Obsolete Product(s) - Obsolete Product(s) ST72325xxx-Auto Watchdog timer (WDG) Doc ID 13770 Rev 3 85/243 10.9 Register description 10.9.1 Control register (WDGCR) WDGCR Reset value: 0111 1111 (7Fh) 76 543 21 0 WDGA T[6:0] RW RW Table 37. WDGCR register description Bit Name Function 7WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. 6:0 T[6:0] 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). Table 38. Watchdog timer register map and reset values Address (Hex.) Register label 76543210 002Ah WDGCR Reset Value WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 |
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