ST72325AR7-Auto datasheet(42/243 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST72325xxx-Auto

42/243

Doc ID 13770 Rev 3

Supply, reset and clock management

6.1

Introduction

The device includes a range of utility features for securing the application in critical

situations (for example in case of a power brown-out), and reducing the number of external

components. An overview is shown in Figure 10.

For more details, refer to the dedicated parametric section.

6.2

Main features

●

Optional PLL for multiplying the frequency by 2 (not to be used with internal RC

oscillator)

●

Reset Sequence Manager (RSM)

●

Multi-oscillator Clock Management (MO)

–

5 crystal/ceramic resonator oscillators

–

1 internal RC oscillator

●

System Integrity Management (SI)

–

Main supply low voltage detection (LVD)

–

Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

supply

–

Clock security system (CSS) with clock filter and backup safe oscillator (enabled

by option byte)

Figure 10.

Clock, reset and supply block diagram

LOW VOLTAGE

DETECTOR

(LVD)

fOSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

VSS

EVD

VDD

RESET SEQUENCE

MANAGER

(RSM)

CLOCK

FILTER

SAFE

OSC

CLOCKSECURITYSYSTEM

(CSS)

OSC2

MAIN CLOCK

CSS Interrupt Request

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD AVD AVD LVD

CSS

WDG

fOSC

fOSC2

(option)

fCPU

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