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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72325AR7-Auto 데이터시트(PDF) 50 Page - STMicroelectronics |
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ST72325AR7-Auto 데이터시트(HTML) 50 Page - STMicroelectronics |
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50 / 243 page  Obsolete Product(s) - Obsolete Product(s) Supply, reset and clock management ST72325xxx-Auto 50/243 Doc ID 13770 Rev 3 Figure 17. Using the voltage detector to monitor the EVD pin (AVDS bit = 1) 6.6.3 Clock security system (CSS) The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and overfrequencies occurring on the main clock source (fOSC). It is based on a clock filter and a clock detection control with an internal safe oscillator (fSFOSC). Clock filter control The PLL has an integrated glitch filtering capability making it possible to protect the internal clock from overfrequencies created by individual spikes. This feature is available only when the PLL is enabled. If glitches occur on fOSC (for example, due to loose connection or noise), the CSS filters these automatically, so the internal CPU frequency (fCPU) continues delivering a glitch-free signal (see Figure 18). Clock detection control If the clock signal disappears (due to a broken or disconnected resonator...), the safe oscillator delivers a low frequency clock signal (fSFOSC) which allows the ST7 to perform some rescue operations. Automatically, the ST7 clock source switches back from the safe oscillator (fSFOSC) if the main clock source (fOSC) recovers. When the internal clock (fCPU) is driven by the safe oscillator (fSFOSC), the application software is notified by hardware setting the CSSD bit in the SICSR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the SICSR register description. VEVD VIT+(EVD) VIT-(EVD) AVDF 0 0 1 IF AVDIE = 1 Vhyst AVD INTERRUPT REQUEST INTERRUPT PROCESS INTERRUPT PROCESS |
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