ST72325AR7-Auto datasheet(127/243 Pages) STMICROELECTRONICS

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ST72325xxx-Auto

Serial peripheral interface (SPI)

Doc ID 13770 Rev 3

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Figure 58.

Single master/single slave application

14.3.2

Slave select management

As an alternative to using the SS pin to control the Slave Select signal, the application can

choose to manage the Slave Select signal by software. This is configured by the SSM bit in

the SPICSR register (see Figure 60)

In software management, the external SS pin is free for other application uses and the

internal SS signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode

●

SS internal must be held high continuously

In Slave mode

There are two cases depending on the data/clock timing relationship (see Figure 59):

If CPHA = 1 (data latched on 2nd clock edge):

●

SS internal must be held low during the entire transmission. This implies that in single

slave applications the SS pin either can be tied to VSS, or made free for standard I/O by

managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR

If CPHA = 0 (data latched on 1st clock edge):

●

SS internal must be held low during byte transmission and pulled high between each

byte to allow the slave to write to the shift register. If SS is not pulled high, a Write

Collision error will occur when the slave writes to the shift register (see Write collision

error (WCOL) on page 132).

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit

LSBit

MSBit

LSBit

Not used if SS is managed

by software

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