ST72325AR7-Auto datasheet(230/243 Pages) STMICROELECTRONICS

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Device configuration and ordering information

ST72325xxx-Auto

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Doc ID 13770 Rev 3

Note:

On the chip, each I/O port has up to eight pads. Pads that are not bonded to external pins

are in input pull-up configuration after reset. The configuration of these pads must be kept at

reset state to avoid added current consumption.

OPT3:1 OSCRANGE[2:0]

Oscillator range

When the resonator oscillator type is selected, these option bits select

the resonator oscillator current source corresponding to the frequency

range of the resonator used. When the external clock source is

selected, these bits are set to medium power (2 ~ 4 MHz).

000: Typ. frequency range = 1 ~ 2 MHz

001: Typ. frequency range = 2 ~ 4 MHz

010: Typ. frequency range = 4 ~ 8 MHz

011: Typ. frequency range = 8 ~ 16 MHz

OPT0

PLLOFF

PLL activation

This option bit activates the PLL which allows multiplication by two of

the main input clock frequency. The PLL is guaranteed only with an

input frequency between 2 and 4 MHz. For this reason the PLL must

not be used with the internal RC oscillator.

0: PLL x2 enabled

1: PLL x2 disabled

Caution: The PLL can be enabled only if the OSCRANGE (OPT3:1) bits

are configured to 2 ~ 4 MHz. Otherwise, the device functionality is not

guaranteed.

Table 147.

Package selection (OPT7)

Version

Selected package

Flash size

PKG1

R/AR

LQFP64

32/48/60 Kbytes

JLQFP44

48/60 Kbytes

16/32 Kbytes

LQFP32

16/32 Kbytes

Table 146.

Option byte 1 bit description (continued)

Bit

Name

Function

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