AT83C5111 datasheet(41/86 Pages) ATMEL

41 / 86 page

AT8xC5111

4190A–8051–11/02

Registers

There are three registers in the module that provide control, status and data storage

functions. These registers are described in the following paragraphs.

Serial Peripheral Control

The Serial Peripheral Control Register does the following:

•

Selects one of the Master clock rates

•

Selects serial clock polarity and phase

•

Enables the SPI module

Table 30 describes this register and explains the use of each bit:

Table 3. Serial Peripheral Control Register

Reset value = 00010100b

7654

3210

SPR2

SPEN

––

CPOL

CPHA

SPR1

SPR0

Bit

Number

Bit

Mnemonic

R/W Mode

Description

7SPR2

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate

6SPEN

Serial Peripheral Enable

Clear to disable the SPI interface

Set to enable the SPI interface

Reserved

Leave this Bit at 0.

Reserved

Leave this Bit at 1.

3CPOL

Clock Polarity

Clear to have the SCK set to ’0’ in idle state

Set to have the SCK set to ’1’ in idle low

2CPHA

Clock Phase

Clear to have the data sampled when the SPSCK leaves the idle

state (see CPOL)

Set to have the data sampled when the SPSCK returns to idle

state (see CPOL)

1SPR1

Serial Peripheral Rate (SPR2:SPR1:SPR0)

000: FCkIdle /2

001: FCkIdle /4

010: FCkIdle /8

011: FCkIdle /16

0SPR0

100: FCkIdle /32

101: FCkIdle /64

110: FCkIdle /128

111: External clock, output of BRG

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