AT83C5111 datasheet(57/86 Pages) ATMEL

57 / 86 page

AT8xC5111

4190A–8051–11/02

Clock Selection

The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in

the AC characteristics section. A prescaler is featured (ADCCLK) to generate the

CONV_CK clock from the oscillator frequency.

Figure 3. A/D Converter Clock

The conversion frequency CONV_CK is derived from the oscillator frequency with the

following formulas:

FCkAdc = FOscOut/(512 - 2*CKRL) , if X2 = 0

= FOscOut

, if X2 = 1

and

FCONV_CK = FCkAdc/(2*PRS), if PRS > 0

FCONV_CK = FCkAdc/256, if PRS = 0

Some examples can be found in the table below:

ADC Standby Mode

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN

in ADCON register.

In this mode the power dissipation is about 1 µW.

Voltage Reference

The Vref pin is used to enter the voltage reference for the A/D conversion.

Best accuracy is obtained with 0.9 V

CC < VREF < VCC.

IT ADC Management

An interrupt end-of-conversion will occur when the bit ADEOC is activated and the bit

EADC is set. To re-arm the interrupt the bit ADEOC must be cleared by software.

Figure 4. ADC Interrupt Structure

Prescaler ADCLK

A/D

Converter

CONV_CK

CKADC

OscOut

MHz

CKRL

CkAdc

Mhz

ADCLK

CONV_CK

khz

Conversion

time

µs

333

250

ADEOC

ADCON.2

EADC

IE1.1

ADCI

AT83C5111 데이터시트(PDF) 57 Page - ATMEL Corporation

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