AT83C5111 datasheet(58/86 Pages) ATMEL

58 / 86 page

AT8xC5111

4190A–8051–11/02

Registers

Table 2. ADCON Register

ADCON (S:F3h)

ADC Control Register

Reset value = X000 0000b

Table 3. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

Reset value = 0000 0000b

7654

3210

QUIETM

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit Number

Bit Mnemonic

Description

7QUIETM

Pseudo Idle mode (best precision)

Set to put in quiet mode during conversion.

Cleared by hardware after completion of the conversion.

6PSIDLE

Pseudo Idle mode (good precision)

Set to put in idle mode during conversion.

Cleared by hardware after completion of the conversion.

5ADEN

Enable/Standby Mode

Set to enable ADC.

Clear for Standby mode (power dissipation 1 µW).

4ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can

generate an interrupt.

Must be cleared by software.

3ADSST

Start and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion.

2 - 0

SCH2:0

Selection of channel to convert

See Table 41.

7654

3210

PRS 6

PRS 5

PRS 4

PRS 3

PRS 2

PRS 1

PRS 0

Bit Number

Bit Mnemonic

Description

–

Reserved

Leave this bit at 0.

6 - 0

PRS6:0

Clock Prescaler

CONV_CK = fCkADC/(2 * PRS)

if PRS = 0, f

CONV_CK = fCkADC/256

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