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XRT75VL00D 데이터시트(PDF) 83 Page - Exar Corporation

부품명 XRT75VL00D
상세설명  E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PDF  92 Pages
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제조업체  EXAR [Exar Corporation]
홈페이지  http://www.exar.com
Logo EXAR - Exar Corporation

XRT75VL00D 데이터시트(HTML) 83 Page - Exar Corporation

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XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
78
• If the LIU has been configured to operate in the Hardware Mode
Then the user should tie the (SR/DR*) pin to "High".
c.
Configure each of the channels within the LIU to operate in the SONET De-Sync Mode
The user can accomplish this by executing either of the following steps.
• If the LIU has been configured to operate in the Host Mode.
Then the user should set Bit D2 (JA0) to "0" and Bit D0 (JA1) to "1", within the Jitter Attenuator Control
Register, as depicted below.
• If the LIU has been configured to operate in the Hardware Mode
Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW".
Once the user accomplishes either of these steps, then the Jitter Attenuator (within the LIU) will be configured
to operate with a very narrow bandwidth.
d.
Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.
The user can accomplish this by executing either the following steps.
• If the LIU has been configured to operate in the Host Mode.
Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted
below.
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06
CHANNEL 1 ADDRESS LOCATION = 0X0E
CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1
BIT 0
Unused
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/
DS3_n
SR/DR_n
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0000
00
1
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7BIT 6BIT 5BIT 4BIT 3
BIT 2BIT 1
BIT 0
Unused
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0000
00
1



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