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STM8S 데이터시트(PDF) 296 Page - STMicroelectronics |
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STM8S 데이터시트(HTML) 296 Page - STMicroelectronics |
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296 / 467 page ![]() Inter-integrated circuit (I2C) interface RM0016 296/467 DocID14587 Rev 14 Master transmitter Following the address transmission and after clearing ADDR, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits until the first data byte is written in the DR register, (see Figure 104Transfer sequencing EV8_1). When the acknowledge pulse is received: • The TXE bit is set by hardware and an interrupt is generated if the ITEVTEN and ITBUFEN bits are set. If TXE is set and a data byte was not written in the DR register before the end of the next data transmission, BTF is set and the interface waits until BTF is cleared, by reading the SR1 register and then writing to the DR register, stretching SCL low. Closing the communication After writing the last byte to the DR register, the STOP bit is set by software to generate a Stop condition (see Figure 104 Transfer sequencing EV8_2). The interface goes automatically back to slave mode (MSL bit cleared). Note: Stop condition should be programmed during EV8_2 event, when either TXE or BTF is set. Figure 104. Transfer sequence diagram for master transmitter 1. Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge, EVx= Event (with interrupt if ITEVTEN=1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address. EV6: ADDR=1, cleared by reading SR1 register followed by reading SR3. EV8_1: TXE=1, shift register empty, data register empty, write DR register. EV8: TXE=1, shift register not empty, data register empty, cleared by writing DR register. EV8_2: TXE=1, BTF = 1, Program STOP request. TXE and BTF are cleared by HW by stop condition EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register. See also:Note 8 on page 311 2. EV8 software sequence must be performed before the end of the current byte transfer. In case EV8 software sequence can not be managed before the end of the current byte transfer, it is recommended to use BTF instead of TXE with the drawback of slowing the communication. 7-bit master transmitter A ..... ..... S Address A Data1 Data2 A DataN A P EV5 EV6 EV8_1 EV8 EV8 EV8 EV8_2 DataN A P EV8_2 Data1 A EV8 EV8 EV8_1 EV6 S EV5 Header A Address A EV9 10-bit master transmitter MS37720V1 |
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