STM8S datasheet(300/467 Pages) STMICROELECTRONICS

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Inter-integrated circuit (I2C) interface

RM0016

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DocID14587 Rev 14

Figure 107. Method 2: transfer sequence diagram for master receiver when N=2

1. Legend:

S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,

EVx= Event (with interrupt if ITEVTEN=1).

EV5: SB=1, cleared by reading SR1 register followed by writing the DR register.

EV6: ADDR1, cleared by reading SR1 register followed by reading SR3.

In 10-bit master receiver mode, this sequence should be followed by writing CR2 with START = 1.

EV6_1: No associated flag event. The acknowledge should be disabled just after EV6, that is after ADDR is

cleared

EV7_3: BTF = 1, program STOP = 1, read DR twice (Read Data1 and Data2) just after programming the

STOP.

EV9: ADD10= 1, cleared by reading SR1 register followed by writing DR register.

2. EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.

3. EV6_1 software sequence must be completed before the ACK pulse of the current byte transfer.

Figure 108. Method 2: transfer sequence diagram for master receiver when N=1

1. Legend:

S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,

EVx= Event (with interrupt if ITEVTEN=1).

EV5: SB=1, cleared by reading SR1 register followed by writing the DR register.

EV6: ADDR =1, cleared by reading SR1 resister followed by reading SR3 register.

EV6_3: ADDR = 1, program ACK = 0, clear ADDR by reading SR1 register followed by reading SR3

EV7: RxNE =1, cleared by reading DR register.

MSv47722V1

EV5

Address

EV6

Data1

Data2

EV7

(1)

EV5

Header

EV9

Address

EV6

EV5

Header

EV6

Data1

Data2

7-bit master receiver

10-bit master receiver

EV6_1

EV7_3

EV6_1

EV7_3

MSv47723V1

EV5

Address

Data1

EV7

EV5

Header

EV9

Address

EV6

EV5

Header

Data1

7-bit master receiver

10-bit master receiver

EV6_3

EV7

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