IS25LP064A-RGLA1 datasheet(19/99 Pages) ISSI

부품명	IS25LP064A-RGLA1

상세설명	3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	99 Pages

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19 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

6.3 READ REGISTER

Read Register format and Bit definitions pertaining to QPI mode are described below.

READ PARAMETER BITS

Table 6.7 defines all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0 (P7, P6, P5) bits

provide a method to set and control driver strength. The Dummy Cycle bits (P4, P3) define how many dummy

cycles are used during various READ modes. The wrap selection bits (P2, P1, P0) define burst length with wrap

around.

The SET READ PARAMETERS Operation (SRP, C0h) is used to set all the Read Register bits, and can thereby

define the output driver strength, number of dummy cycles used during READ modes, burst length with wrap

around.

Table 6.7 Read Parameter Table

ODS2

ODS1

ODS0

Dummy

Cycles

Dummy

Cycles

Wrap

Enable

Burst

Length

Burst

Length

Default (Volatile)

Table 6.8 Burst Length Data

8 bytes

16 bytes

32 bytes

64 bytes

Table 6.9 Wrap Function

Wrap around boundary

Whole array regardless of P1 and P0 value

Burst Length set by P1 and P0

IS25LP064A-RGLA1 데이터시트(PDF) 19 Page - Integrated Silicon Solution, Inc