IS25LP064A-RGLA1 datasheet(78/99 Pages) ISSI

78 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

FAST READ QUAD IO DTR QPI MODE OPERATION (FRQDTR QPI, EDh)

The FRQDTR QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are

required, while the FRQDTR instruction requires that the byte-long instruction code is shifted into the device

only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQDTR QPI instruction.

In addition, subsequent address and data out are shifted in/out via all four IO lines like the FRQDTR instruction.

In fact, except for the command cycle, the FRQDTR QPI operation is exactly same as the FRQDTR.

The sequence of issuing FRQDTR QPI instruction is: CE# goes low  Sending FRQDTR QPI instruction (4-bit

per clock)  24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  3 dummy clocks (configurable,

default is 3 clocks)  Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  End FRQDTR QPI

operation by driving CE# high at any time during data out.

If AXh (

where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read

operation mode which enables subsequent FRQDTR QPI execution skips command code. It saves cycles as

described in Figure 8.60. When the code is different from AXh, the device exits the AX read operation. After

finishing the read operation, device becomes ready to receive a new command.

If the FRQDTR QPI instruction is issued while a Program/Erase/Write Status Register cycle is in progress

(WIP=1), the instruction will be rejected without any effect on the current cycle.

Figure 8.61 FRQDTR QPI Sequence (with command decode cycles)

Instruction

= EDh

CE #

SCK

3-byte Address

Mode 3

Mode 0

20 16 12

5 1

21 17 13

4 0

IO0

IO1

22 18 14

23 19 15

8 4 0

9 5 1

10 6 2

11 7 3

3 Dummy Cycles

IO2

IO3

6 2

7 3

5 1

4 0

6 2

7 3

Data

Out

Data

Out

5 1

4 0

6 2

7 3

Mode Bits

...

5 1

4 0

6 2

7 3

Data

Out

5 1

4 0

6 2

7 3

Data

Out

5 1

4 0

6 2

7 3

Data

Out

...

Notes:

1. If the mode bits=AXh (

where X is don’t care), it can execute the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles

are same, then X should be Hi-Z.

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