IS25LP064A-RGLA1 datasheet(67/99 Pages) ISSI

부품명	IS25LP064A-RGLA1

상세설명	3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	99 Pages

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제조업체	ISSI [Integrated Silicon Solution, Inc]

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67 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

8.33 INFORMATION ROW ERASE OPERATION (IRER, 64h)

Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the

operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is

automatically reset after the completion of the operation.

The sequence of IRER operation: Pull CE# low to select the device  Send IRER instruction code  Send

three address bytes  Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE#

is pulled high, Erase operation will begin immediately. The internal control logic automatically handles the erase

voltage and timing. Refer to Figure 8.49 for IRER Sequence.

Figure 8.52 IRER (Information Row Erase) Sequence

Instruction = 64h

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

IS25LP064A-RGLA1 데이터시트(PDF) 67 Page - Integrated Silicon Solution, Inc