IS25LP064A-RGLA1 datasheet(69/99 Pages) ISSI

69 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

8.35 INFORMATION ROW READ OPERATION (IRRD, 68h)

The IRRD instruction is used to read memory data at up to a 133MHz clock.

The IRRD instruction code is followed by three address bytes (A23 - A0) and a dummy byte, transmitted via the

SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out

on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.

The address is automatically incremented by one after each byte of data is shifted out. Once the address

reaches the last address of each 256 byte Information Row, the next address will not be valid and the data of

the address will be garbage data. It is recommended to repeat four times IRRD operation that reads 256 byte

with a valid starting address of each Information Row in order to read all data in the 4 x 256 byte Information

Row array. The IRRD instruction is terminated by driving CE# high (VIH).

If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not have any effects on the current cycle.

The sequence of IRRD instruction is same as FAST READ except for the instruction code. IRRD QPI sequence

is also same as FAST READ QPI except for the instruction code. Refer to the FAST READ QPI operation.

Figure 8.54 IRRD (Information Row Read) Sequence

Instruction = 68h

Dummy Cycles

CE #

SCK

...

Mode 3

Mode 0

3 Byte Address

Data Out

...

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