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IS25LP064A-RGLA1 데이터시트(PDF) 26 Page - Integrated Silicon Solution, Inc

부품명 IS25LP064A-RGLA1
상세설명  3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  99 Pages
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제조업체  ISSI [Integrated Silicon Solution, Inc]
홈페이지  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP064A-RGLA1 데이터시트(HTML) 26 Page - Integrated Silicon Solution, Inc

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IS25LP064A/032A
Integrated Silicon Solution, Inc.- www.issi.com
26
Rev. A
11/06/2015
8.2 FAST READ OPERATION (FRD, 0Bh)
The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from
the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling
edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST
READ instruction is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
Instruction = 0Bh
3-byte Address
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
...
7
6
CE #
SCK
SI
5
3
2
SO
4
1
Data Out
31
CE #
SCK
SI
3
2
SO
1
0
High Impedance
30
29
...
0
1
2
3
4
5
6
7
8
9
10
...
Mode 3
Mode 0
tV
Dummy Cycles
0
...



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