IS25LP064A-RGLA1 datasheet(71/99 Pages) ISSI

71 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

FAST READ DTR QPI MODE OPERATION (FRDTR QPI, 0Dh)

The FRDTR QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are

required, while the FRDTR instruction requires that the byte-long instruction code is shifted into the device only

via IO0 line in eight clocks. In addition, subsequent address and data out are shifted in/out via all four IO lines

unlike the FRDTR instruction. Eventually this operation is same as the FRQDTR QPI, but the only different thing

is that AX mode is not available in the FRDTR QPI operation.

The sequence of issuing FRDTR QPI instruction is: CE# goes low  Sending FRDTR QPI instruction (4-bit per

clock)  24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  3 dummy clocks (configurable,

default is 3 clocks)  Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  End FRDTR QPI operation

by driving CE# high at any time during data out.

If the FRDTR QPI instruction is issued while a Program/Erase/Write Status Register cycle is in progress

(WIP=1), the instruction will be rejected without any effect on the current cycle.

Figure 8.56 FRDTR QPI Sequence

Instruction

= 0Dh

CE #

SCK

3-byte Address

Mode 3

Mode 0

20 16 12

5 1

21 17 13

4 0

IO0

IO1

22 18 14

23 19 15

8 4

9 5

10 6

11 7

3 Dummy Cycles

IO2

IO3

6 2

7 3

5 1

4 0

6 2

7 3

Data

Out

Data

Out

...

5 1

4 0

6 2

7 3

Data

Out

5 1

4 0

6 2

7 3

Data

Out

5 1

4 0

6 2

7 3

Data

Out

...

Notes:

1. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.

2. Sufficient dummy cycles are required to avoid I/O contention.

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