K32L2AX datasheet(15/96 Pages) NXP

15 / 96 page

Table 5. Chip power modes (continued)

Chip mode

Description

Core mode

Normal

recovery

method

STOP (Normal

Stop) - via WFI

Places chip in static state. Lowest power mode that retains all

registers while maintaining LVD protection.

• NVIC is disabled.

• AWIC is used to wake up from interrupt.

• Peripheral clocks are stopped.

Sleep Deep

Interrupt

VLPR (Very

Low-Power

Run)

On-chip voltage regulator is in a low-power mode that supplies only

enough power to run the chip at a reduced frequency.

• Reduced frequency Flash access mode (1 MHz)

• LVD off

• In BLPI clock mode, only the fast internal reference oscillator is

available to provide a low power nominal 4 MHz source for the

core with the nominal bus and flash clock required to be <800

kHz

• Alternatively, BLPE clock mode can be used with an external

clock or the crystal oscillator providing the clock source.

Run

—

VLPW (Very

Low-Power

Wait) -via WFI

Same as VLPR but with the core in Sleep mode to further reduce

power.

• NVIC remains sensitive to interrupts (FCLK = ON).

• On-chip voltage regulator is in a low-power mode that supplies

only enough power to run the chip at a reduced frequency.

Sleep

Interrupt

VLPS (Very

Low-Power

Stop)-via WFI

Places chip in static state with LVD operation off. Lowest power mode

with ADC and pin interrupts functional.

• Peripheral clocks are stopped, but OSC, LPTMR,LPUART,

RTC, CMP, TSI can be used.

• TPM and UART can optionally be enabled if their clock source

is enabled.

• NVIC is disabled (FCLK = OFF); AWIC is used to wake up from

interrupt.

• On-chip voltage regulator is in a low-power mode that supplies

only enough power to run the chip at a reduced frequency.

• All SRAM is operating (content retained and I/O states held).

Sleep Deep

Interrupt

LLS3 (Low-

Leakage Stop3)

State retention power mode

• Most peripherals are in state retention mode (with clocks

stopped), but OSC, LLWU,LPTMR, RTC, CMP, TSI can be

used.

• NVIC is disabled; LLWU is used to wake up.

NOTE:

The LLWU interrupt must not be masked

by the interrupt controller to avoid a

scenario where the system does not fully

exit stop mode on an LLS recovery

• All SRAM is operating (content retained and I/O states held).

Sleep Deep

Wake-up

Interrupt1

LLS2 (Low-

Leakage Stop2)

State retention power mode

• Most peripherals are in state retention mode (with clocks

stopped), but OSC, LLWU,LPTMR, RTC, CMP, TSI can be

used.

• NVIC is disabled; LLWU is used to wake up.

NOTE:

The LLWU interrupt must not be masked

by the interrupt controller to avoid a

Sleep Deep

Wake-up

Interrupt1

Table continues on the next page...

Overview

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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