K32L2AX datasheet(43/96 Pages) NXP

43 / 96 page

Table 16. Power consumption operating behaviors (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

IDD_VLLS2

Very-low-leakage stop mode 2 current

at 3.0 V

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

—

1.8

3.3

6.1

10.4

21.6

3.4

6.8

14.5

26.4

54.4

μA

IDD_VLLS1

Very-low-leakage stop mode 1 current

at 3.0V

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

—

0.65

1.1

2.1

3.6

8.5

0.88

1.6

3.3

21.0

32.2

μA

IDD_VLLS0

Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 0) at 3.0

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

—

372.0

768.6

1734

3291

8025

598

1331

3038

20575

27560

IDD_VLLS0

Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 1) at 3.0

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

—

94.1

480.9

1416

2970

7642

311

1024

2760

19574

27325

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

2. 96 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_HCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks disabled by clearing all xxDIV3, xxDIV2, and xxDIV1 in SCG_SOSCDIV and

SCG_SPLLDIV registers. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and

SCG_SIRCCSR[SIRCEN].

3. 96 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_HCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks except USB = 24 MHz from SPLLDIV3_CLK. USB functional clock = 48 MHz

from SPLLDIV1_CLK. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].

General

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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