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K32L2AX 데이터시트(PDF) 79 Page - NXP Semiconductors

부품명 K32L2AX
상세설명  K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM
PDF  96 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
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K32L2AX 데이터시트(HTML) 79 Page - NXP Semiconductors

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8.8.4 LPSPI switching specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The following tables provide timing characteristics for classic SPI timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI
pins.
NOTE
• Slew rate disabled pads are those pins with
PORTx_PCRn[SRE] bit cleared. Slew rate enabled pads
are those pins with PORTx_PCRn[SRE] bit set.
• To achieve high bit rate, it is recommended to use fast
pins (PTE20, PTE21, PTE22, PTE23, PTD4, PTD5,
PTD6, and PTD7) and/or high drive pins (PTC3, PTC4,
PTD4, PTD5, PTD6, and PTD7).
Table 48. LPSPI master mode timing on slew rate disabled pads
Num.
Symbol
Description
Min.
Max.
Unit
Note
1
fop
Frequency of operation
fperiph/2048
fperiph/2
Hz
1
2
tSPSCK
SPSCK period
2 x tperiph
2048 x
tperiph
ns
2
3
tLead
Enable lead time
1/2
—
tSPSCK
—
4
tLag
Enable lag time
1/2
—
tSPSCK
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
ns
—
6
tSU
Data setup time (inputs)
18
—
ns
—
7
tHI
Data hold time (inputs)
0
—
ns
—
8
tv
Data valid (after SPSCK edge)
—
15
ns
—
9
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
1. fperiph is the LPSPI peripheral functional clock.
2. tperiph = 1/fperiph
Peripheral operating requirements and behaviors
K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021
79
NXP Semiconductors



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