K32L2AX datasheet(16/96 Pages) NXP

16 / 96 page

Table 5. Chip power modes (continued)

Chip mode

Description

Core mode

Normal

recovery

method

scenario where the system does not fully

exit stop mode on an LLS recovery

• 64 KB SRAM retained, internal logic and I/O states are

retained.

VLLS3 (Very

Low-Leakage

Stop3)

• Most peripherals are disabled (with clocks stopped), but OSC,

LLWU, LPTMR, RTC, CMP, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• SRAM_U and SRAM_L remain powered on (content retained

and I/O states held).

Sleep Deep

Wake-up

Reset-1

VLLS2 (Very

Low-Leakage

Stop2)

• Most peripherals are disabled (with clocks stopped), but OSC,

LLWU, LPTMR, RTC, CMP, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• 64K of SRAM_U remains powered on (content retained and I/O

states held).

Sleep Deep

Wake-up

Reset-1

VLLS1 (Very

Low-Leakage

Stop1)

• Most peripherals are disabled (with clocks stopped), but OSC,

LLWU, LPTMR, RTC, CMP, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• All of SRAM_U and SRAM_L are powered off.

• The 32-byte system register file remains powered for customer-

critical data

• The 16-byte system register file remains powered for customer-

critical data

Sleep Deep

Wake-up

Reset-1

VLLS0 (Very

Low-Leakage

Stop 0)

• Most peripherals are disabled (with clocks stopped), but LLWU,

LPTMR, RTC, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• All of SRAM_U and SRAM_L are powered off.

• The 32-byte system register file remains powered for customer-

critical data

• The 16-byte system register file remains powered for customer-

critical data

• LPO disabled, optional POR brown-out detection

Sleep Deep

Wake-up

Reset-1

1. Resumes Normal Run mode operation by executing the LLWU interrupt service routine.

2.1.9 LLWU

The device uses the following internal peripheral and external pin inputs as wakeup

sources to the LLWU module. LLWU_Px are external pin inputs, and

LLWU_M0IFM7IF are connections to the internal peripheral interrupt flags.

NOTE

In addition to the LLWU wakeup sources, the device also

wakes from low power modes when NMI or RESET pins are

enabled and the respective pin is asserted.

Overview

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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