K32L2AX datasheet(74/96 Pages) NXP

74 / 96 page

The following table defines the general timing requirements for the EMV SIM

interface.

Table 43. Timing Specifications, High Drive Strength

Parameter

Symbol

Min

Max

Unit

EMV SIM clock frequency (EMVSIMn_CLK)1

Sfreq

MHz

EMV SIM clock rise time (EMVSIMn_CLK)2

Srise

—

0.08 × (1/Sfreq)

EMV SIM clock fall time (EMVSIMn_CLK)2

Sfall

—

0.08 × (1/Sfreq)

EMV SIM input transition time (EMVSIMn_IO,

EMVSIMn_PD)

Stran

EMV SIM I/O rise time / fall time (EMVSIMn_IO)3

Tr/Tf

—

0.8

μs

EMV SIM RST rise time / fall time (EMVSIMn_RST)4

Tr/Tf

—

0.8

μs

1. 50% duty cycle clock,

2. With C = 50 pF

3. With Cin = 30 pF, Cout = 30 pF,

4. With Cin = 30 pF,

8.8.1.1 EMV SIM Reset Sequences

Smart cards may have internal reset, or active low reset. The following subset describes

the reset sequences in these two cases.

8.8.1.1.1 Smart Cards with Internal Reset

Following figure shows the reset sequence for Smart cards with internal reset. The reset

sequence comprises the following steps:

• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)

• After 200 clock cycles, EMVSIMn_IO must be asserted.

• The card must send a response on EMVSIMn_IO acknowledging the reset between

400–40000 clock cycles after T0.

Peripheral operating requirements and behaviors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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