HCS08 datasheet(192/374 Pages) NXP

192 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

192

Freescale Semiconductor

•

CLKS bits are written to 10

•

IREFS bit is written to 0

•

PLLS bit is written to 0

•

RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz

•

LP bit is written to 0

In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The

external reference clock which is enabled can be an external crystal/resonator or it can be another external

clock source.The FLL clock is controlled by the external reference clock, and the FLL clock frequency

locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from

the FLL and the PLL is disabled in a low power state.

NOTE

It is possible to briefly operate in FBE mode with an FLL reference clock

frequency that is greater than the specified maximum frequency. This can be

necessary in applications that operate in PEE mode using an external crystal

with a frequency above 5 MHz. Please see 12.5.2.4, “Example # 4: Moving

from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz

for a detailed example.

12.4.1.5

PLL Engaged External (PEE)

The PLL engaged external (PEE) mode is entered when all the following conditions occur:

•

CLKS bits are written to 00

•

IREFS bit is written to 0

•

PLLS bit is written to 1

•

RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz

In PLL engaged external mode, the MCGOUT clock is derived from the PLL clock which is controlled by

the external reference clock. The external reference clock which is enabled can be an external

crystal/resonator or it can be another external clock source The PLL clock frequency locks to a

multiplication factor, as selected by the VDIV bits, times the reference frequency, as selected by the RDIV

bits. If BDM is enabled then the MCGLCLK is derived from the DCO (open-loop mode) divided by two.

If BDM is not enabled then the FLL is disabled in a low power state.

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