HCS08 datasheet(193/374 Pages) NXP

193 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

193

12.4.1.6

PLL Bypassed External (PBE)

In PLL bypassed external (PBE) mode, the MCGOUT clock is derived from the external reference clock

and the PLL is operational but its output clock is not used. This mode is useful to allow the PLL to acquire

its target frequency while the MCGOUT clock is driven from the external reference clock.

The PLL bypassed external mode is entered when all the following conditions occur:

•

CLKS bits are written to 10

•

IREFS bit is written to 0

•

PLLS bit is written to 1

•

RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz

•

LP bit is written to 0

In PLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The

external reference clock which is enabled can be an external crystal/resonator or it can be another external

clock source. The PLL clock frequency locks to a multiplication factor, as selected by the VDIV bits, times

the reference frequency, as selected by the RDIV bits. If BDM is enabled then the MCGLCLK is derived

from the DCO (open-loop mode) divided by two. If BDM is not enabled then the FLL is disabled in a low

power state.

12.4.1.7

Bypassed Low Power Internal (BLPI)

The bypassed low power internal (BLPI) mode is entered when all the following conditions occur:

•

CLKS bits are written to 01

•

IREFS bit is written to 1

•

PLLS bit is written to 0 or 1

•

LP bit is written to 1

•

BDM mode is not active

In bypassed low power internal mode, the MCGOUT clock is derived from the internal reference clock.

The PLL and the FLL are disabled at all times in BLPI mode and the MCGLCLK will not be available for

BDC communications If the BDM becomes active the mode will switch to one of the bypassed internal

modes as determined by the state of the PLLS bit.

12.4.1.8

Bypassed Low Power External (BLPE)

The bypassed low power external (BLPE) mode is entered when all the following conditions occur:

•

CLKS bits are written to 10

•

IREFS bit is written to 0

•

PLLS bit is written to 0 or 1

•

LP bit is written to 1

•

BDM mode is not active

HCS08 데이터시트(PDF) 193 Page - NXP Semiconductors

HCS08 데이터시트(HTML) 193 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL