IMX6SDLCEC datasheet(52/169 Pages) NXP

52 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.8.4

MLB I/O Differential Output Impedance

Table 38 shows MLB I/O differential output impedance of the i.MX 6Solo/6DualLite processors.

4.9

System Modules Timing

This section contains the timing and electrical parameters for the modules in each i.MX 6Solo/6DualLite

processor.

4.9.1

Reset Timings Parameters

Figure 11 shows the reset timing and Table 39 lists the timing parameters.

Figure 11. Reset Timing Diagram

4.9.2

WDOG Reset Timing Parameters

Figure 12 shows the WDOG reset timing and Table 40 lists the timing parameters.

Figure 12. WDOG1_B Timing Diagram

NOTE

XTALOSC_RTC_XTALI is approximately 32 kHz.

XTALOSC_RTC_XTALI cycle is one period or approximately 30

μs.

Table 38. MLB I/O Differential Output Impedance

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Differential Output Impedance

—

1.6

—

Table 39. Reset Timing Parameters

Parameter

Min

Max

Unit

CC1

Duration of SRC_POR_B to be qualified as valid.

—

XTALOSC_RTC_XTALI cycle

Table 40. WDOG1_B Timing Parameters

Parameter

Min

Max

Unit

CC3

Duration of WDOG1_B Assertion

—

XTALOSC_RTC_XTALI cycle

SRC_POR_B

CC1

(Input)

WDOG1_B

CC3

(Output)

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