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IMX6SDLCEC 데이터시트(PDF) 1 Page - NXP Semiconductors |
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IMX6SDLCEC 데이터시트(HTML) 1 Page - NXP Semiconductors |
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1 / 169 page ![]() NXP Semiconductors Data Sheet: Technical Data Document Number: IMX6SDLCEC Rev. 9, 11/2018 Package Information Plastic Package BGA Case 2240 21 x 21 mm, 0.8 mm pitch Ordering Information See Table 1 on page 3 NXP Reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products MCIMX6SxDxxxxxB MCIMX6SxDxxxxxC MCIMX6SxDxxxxxD MCIMX6UxDxxxxxB MCIMX6UxDxxxxxC MCIMX6UxDxxxxxD MCIMX6SxExxxxxB MCIMX6SxExxxxxC MCIMX6SxExxxxxD MCIMX6UxExxxxxB MCIMX6UxExxxxxC MCIMX6UxExxxxxD 1 Introduction The i.MX 6Solo/6DualLite processors represent the latest achievement in integrated multimedia-focused products offering high performance processing with lower cost, as well as optimization for low power consumption. The processors feature advanced implementation of single/dual Arm® Cortex®-A9 core, which operates at speeds of up to 1 GHz. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 32/64-bit DDR3/DDR3L/LPDDR2-800 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth®, GPS, hard drive, displays, and camera sensors. The i.MX 6Solo/6DualLite processors are specifically useful for applications such as: • Web and multimedia tablets • Web and multimedia tablets i.MX 6Solo/6DualLite Applications Processors for Consumer Products 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 Updated Signal Naming Convention . . . . . . . . . . . .9 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1 Special Signal Considerations . . . . . . . . . . . . . . . .21 3.2 Recommended Connections for Unused Analog Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .23 4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .23 4.2 Power Supplies Requirements and Restrictions . .33 4.3 Integrated LDO Voltage Regulator Parameters . . .34 4.4 PLL’s Electrical Characteristics . . . . . . . . . . . . . . .36 4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .38 4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .39 4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .44 4.8 Output Buffer Impedance Parameters . . . . . . . . . .49 4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .52 4.10 General-Purpose Media Interface (GPMI) Timing .64 4.11 External Peripheral Interface Parameters . . . . . . .72 5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .134 5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .134 5.2 Boot Device Interface Allocation . . . . . . . . . . . . .135 6 Package Information and Contact Assignments . . . . . .136 6.1 Updated Signal Naming Convention . . . . . . . . . .136 6.2 21x21 mm Package Information. . . . . . . . . . . . . .137 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 |
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