IMX6SDLCEC datasheet(79/169 Pages) NXP

79 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

4.11.4

Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

Timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single

Data Rate) timing, eMMC4.4/4.41 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.

4.11.4.1

SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 40 depicts the timing of SD/eMMC4.3, and Table 52 lists the SD/eMMC4.3 timing characteristics.

Figure 40.

SD/eMMC4.3 Timing

Table 52.

SD/eMMC4.3 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP

400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP

25/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP

20/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

7—

SD3

Clock High Time

tWH

7—

SD4

Clock Rise Time

tTLH

—3

SD5

Clock Fall Time

tTHL

—3

uSDHC Output/Card Inputs SDx_CMD, SDx_DATAx (Reference to CLK)

SD6

uSDHC Output Delay

tOD

-6.6

3.6

SD1

SD3

SD5

SD4

SD7

SDx_CLK

SD2

SD8

SD6

Output from uSDHC to card

Input from card to uSDHC

SDx_DATA[7:0]

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