IMX6SDLCEC datasheet(84/169 Pages) NXP

84 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

4.11.5.1.4

MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 46 shows MII asynchronous input timings. Table 58 describes the timing parameters (M10–M15)

shown in the figure.

Figure 46. MII Serial Management Channel Timing Diagram

Table 57. MII Asynchronous Inputs Signal Timing

Characteristic

Min

Max

Unit

M91

ENET_CRS to ENET_COL minimum pulse width

1.5

—

ENET_TX_CLK period

Table 58. MII Serial Management Channel Timing

Characteristic

Min

Max

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

0—

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—5

M12

ENET_MDIO (input) to ENET_MDC rising edge setup

—

M13

ENET_MDIO (input) to ENET_MDC rising edge hold

—

M14

ENET_MDC pulse width high

40%

60%

ENET_MDC period

M15

ENET_MDC pulse width low

40%

60%

ENET_MDC period

ENET_MDC (output)

ENET_MDIO (output)

M14

M15

M10

M11

M12

M13

ENET_MDIO (input)

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