IMX6SDLCEC datasheet(74/169 Pages) NXP

74 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.11.2.2

ECSPI Slave Mode Timing

Figure 37 depicts the timing of ECSPI in slave mode. Table 50 lists the ECSPI slave mode timing

characteristics.

Figure 37. ECSPI Slave Mode Timing Diagram

Table 50. ECSPI Slave Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1 ECSPIx_SCLK Cycle Time–Read

ECSPIx_SCLK Cycle Time–Write

tclk

—ns

CS2 ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

tSW

21.5

—ns

CS4 ECSPIx_SS_B pulse width

tCSLH

Half ECSPIx_SCLK period

—

CS5 ECSPIx_SS_B Lead Time (CS setup time)

tSCS

5—

CS6 ECSPIx_SS_B Lag Time (CS hold time)

tHCS

5—

CS7 ECSPIx_MOSI Setup Time

tSmosi

4—

CS8 ECSPIx_MOSI Hold Time

tHmosi

4—

CS9 ECSPIx_MISO Propagation Delay (CLOAD =20pF)

•

tPDmiso

419

CS1

CS7

CS8

CS2

CS4

CS6

CS5

CS9

ECSPIx_SCLK

ECSPIx_SS_B

ECSPIx_MISO

ECSPIx_MOSI

Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be con-

nected between a single master and a single slave.

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