전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

IMX6SDLCEC 데이터시트(PDF) 64 Page - NXP Semiconductors

부품명 IMX6SDLCEC
상세설명  i.MX 6Solo/6DualLite Applications Processors for Consumer Products
PDF  169 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX6SDLCEC 데이터시트(HTML) 64 Page - NXP Semiconductors

Back Button IMX6SDLCEC Datasheet HTML 60Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 61Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 62Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 63Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 64Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 65Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 66Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 67Page - NXP Semiconductors IMX6SDLCEC Datasheet HTML 68Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 64 / 169 page
background image
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018
64
NXP Semiconductors
Electrical Characteristics
4.10
General-Purpose Media Interface (GPMI) Timing
The i.MX 6Solo/6DualLite GPMI controller is a flexible interface NAND Flash controller with 8-bit data
width, up to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing
mode separately described in the following subsections.
4.10.1
Asynchronous Mode AC Timing (ONFI 1.0 Compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 25 through Figure 28
depicts the relative timing between GPMI signals at the module level for different operations under
asynchronous mode. Table 46 describes the timing parameters (NF1–NF17) that are shown in the figures.
Figure 25. Command Latch Cycle Timing Diagram
Table 45. i.MX 6DualLite Supported DDR3/DDR3L/LPDDR2 Configurations
Parameter
LPDDR2
(Dual channel)
LPDDR2
(Single channel)
DDR3
DDR3L
Clock frequency
400 MHz
400 MHz
400 MHz
400 MHz
Bus width
32-bit per channel
16/32-bit
16/32/64-bit
16/32/64-bit
Channel
Dual
Single
Single
Single
Chip selects
2 per channel
2
2
2
Command
NF8
NF9
NF7
NF6
NF5
NF2
NF1
NF3
NF4



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com