IMX6SDLCEC datasheet(114/169 Pages) NXP

114 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

114

NXP Semiconductors

Electrical Characteristics

Figure 81. DATA and FLAG Signal Timing

4.11.14 MediaLB (MLB) Characteristics

4.11.14.1 MediaLB (MLB) DC Characteristics

Table 73 lists the MediaLB 3-pin interface electrical characteristics.

tEageSepTx, min

Minimum allowed separation of signal transitions at transmitter

package pins, including all timing defects, for example, jitter

and skew, inside the transmitter.

400 ns

4.00 ns

2.00 ns

tEageSepRx, min

Minimum separation of signal transitions, measured at the

receiver package pins, including all timing defects, for example,

jitter and skew, inside the receiver.

350 ns

3.5 ns

1.75 ns

Table 73. MediaLB 3-Pin Interface Electrical DC Specifications

Parameter

Symbol

Test Conditions

Min

Max

Unit

Maximum input voltage

—

3.6

Low level input threshold

VIL

——

0.7

High level input threshold

VIH

See Note1

1 Higher V

IH thresholds can be used; however, the risks associated with less noise margin in the system must be

evaluated and assumed by the customer.

1.8

—

Low level output threshold

VOL

IOL = 6 mA

—

0.4

High level output threshold

VOH

IOH = -6 mA

2.0

—

Input leakage current

0 < Vin < VDD

—

±10

μA

Table 72. DATA and FLAG Timing (continued)

Parameter

Description

1 Mbit/s

100 Mbit/s

200 Mbit/s

1 This case shows that the DATA signal has slowed down more compared to the FLAG signal

2 This case shows that the FLAG signal has slowed down more compared to the DATA signal.

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