IMX6SDLCEC datasheet(125/169 Pages) NXP

125 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

125

4.11.19.2 SSI Receiver Timing with Internal Clock

Figure 92 depicts the SSI receiver internal clock timing and Table 83 lists the timing parameters for the

receiver timing with the internal clock.

Figure 92. SSI Receiver Internal Clock Timing Diagram

Table 83. SSI Receiver Timing with Internal Clock

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

AUDx_TXC/AUDx_RXC clock period

81.4

—

SS2

AUDx_TXC/AUDx_RXC clock high period

36.0

—

SS3

AUDx_TXC/AUDx_RXC clock rise time

—

6.0

SS4

AUDx_TXC/AUDx_RXC clock low period

36.0

—

SS5

AUDx_TXC/AUDx_RXC clock fall time

—

6.0

SS7

AUDx_RXC high to AUDx_TXFS (bl) high

—

15.0

SS9

AUDx_RXC high to AUDx_TXFS (bl) low

—

15.0

SS11

AUDx_RXC high to AUDx_TXFS (wl) high

—

15.0

SS13

AUDx_RXC high to AUDx_TXFS (wl) low

—

15.0

SS20

AUDx_RXD setup time before AUDx_RXC low

10.0

—

SS21

AUDx_RXD hold time after AUDx_RXC low

0.0

—

SS50

SS48

SS1

SS4

SS2

SS51

SS20

SS21

SS49

SS7

SS9

SS11

SS13

SS47

SS3

SS5

AUDx_TXC

(Output)

AUDx_TXFS (bl)

(Output)

AUDx_TXFS (wl)

(Output)

AUDx_RXD

(Input)

AUDx_RXC

(Output)

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