HCS08 datasheet(150/316 Pages) NXP

150 / 316 page

Internal Clock Source (S08ICSV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

150

Freescale Semiconductor

Figure 10-2. Internal Clock Source (ICS) Block Diagram

10.1.4

Modes of Operation

There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.

10.1.4.1

FLL Engaged Internal (FEI)

In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL

which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.

10.1.4.2

FLL Engaged External (FEE)

In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an

external reference clock. The BDC clock is supplied from the FLL.

10.1.4.3

FLL Bypassed Internal (FBI)

In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is

bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied

from the FLL.

DCO

Filter

RDIV

TRIM

/ 2

External Reference

IREFS

Clock Source

Block

CLKS

n=0-7

/ 2n

n=0-3

/ 2n

Internal

Reference

Clock

BDIV

ICSLCLK

ICSOUT

ICSIRCLK

EREFS

RANGE

EREFSTEN

HGO

Optional

IREFSTEN

ICSERCLK

Internal Clock Source Block

ICSFFCLK

ERCLKEN

IRCLKEN

DCOOUT

FLL

RDIV_CLK

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