HCS08 datasheet(81/316 Pages) NXP

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Chapter 6 Parallel Input/Output Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

6.6.1.3

Port A Pull Enable Register (PTAPE)

6.6.1.4

Port A Slew Rate Enable Register (PTASE)

321

PTAPE3

PTAPE2

PTAPE1

PTAPE0

Reset:

000

Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)

Table 6-4. PTAPE Register Field Descriptions

Field

Description

5:4

Reserved

Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.

3:0

PTAPE[3:0]

Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down

device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no

effect and the internal pull devices are disabled.

0 Internal pull-up/pull-down device disabled for port A bit n.

1 Internal pull-up/pull-down device enabled for port A bit n.

321

PTASE3

PTASE2

PTASE1

PTASE0

Reset:

000

Figure 6-6. Slew Rate Enable for Port A Register (PTASE)

Table 6-5. PTASE Register Field Descriptions

Field

Description

5:4

Reserved

Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.

3:0

PTASE[3:0]

Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control

is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.

0 Output slew rate control disabled for port A bit n.

1 Output slew rate control enabled for port A bit n.

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